(1) Field of the Invention
The invention relates to a constant on time control circuit and a DC to DC converting circuit.
(2) Description of the Prior Art
FIG. 1 is a schematic diagram of a DC to DC converting circuit with low voltage ripple and high frequency hysteretic disclosed in U.S. Pat. No. 6,369,555. The DC to DC converting circuit comprises a buffer circuit 2, a hysteresis comparator 4, a feedback circuit 6 and a driving circuit 8. The feedback circuit 6 is coupled to an output end of the hysteresis comparator 4 and provides a feedback signal VRAMP. The input end of the buffer circuit 2 receives a superimposed signal VREF of the feedback signal VRAMP and a reference signal VREF, i.e., VREF=VREF+VRAMP. Input ends of the hysteresis comparator 4 are respectively coupled to an output end of the buffer circuit 2 and an output voltage VOUT, and the output end thereof is coupled to the driving circuit 8. The driving circuit 8 may be a power transistor, coupled to an input voltage VIN and an LC filter 12. The LC filter 12 provides the output voltage VOUT.
Because the noise affects the limit of detecting voltage, a hysteresis window of the hysteresis comparator 4 must be setting wider. Thus, the voltage ripple on the output voltage VOUT can't be eliminated, and particularly the voltage ripple is more obvious with the output voltage VOUT being lower.
The constant on time control loop is another new feedback control mechanism. The constant on time control loop superimposes a voltage ripple generated by an equivalent series resistance (ESR) of the output capacitance into the feedback signal to inhibit the voltage ripple on the output voltage. Therefore, the output capacitance for the constant on time control loop must be provided with the bigger equivalent series resistance, and an operation frequency thereof can't been set high.
For solving the above mentioned problems, the U.S. Pat. No. 7,482,793 discloses a DC to DC converting circuit with constant on time and minimum off-time feedback control loop. FIG. 2 is a schematic diagram of a DC to DC converting circuit of the U.S. Pat. No. 7,482,793. The DC to DC converting circuit comprises a buck converting controller 100 and is coupled to an LC filter. The buck converting controller 100 receives an input voltage VIN at a terminal end 102, and provides a switching output voltage VSW at a terminal end 104 to the LC filter that is composed by an inductance L1 and an output capacitance COUT. The LC filter generates an output voltage VOUT at a terminal end 114 for driving a load 116. The output capacitance COUT has a smaller equivalent series resistance ESR. The buck converting controller 100 executes the feedback control with the constant on time and minimum off-time feedback control loop. Power transistors M1 and M2 are coupled in series between the input voltage VIN (terminal end 102) and the ground (terminal end PGND), and controlled by a driving circuit 134. A connection node 122 of the power transistors M1 and M2 generates the switching output voltage VSW, and is coupled to the LC filter through a terminal end SW. The buck converting controller 100 has two separate ground connection terminal ends PGND and SGND for avoiding the noise due to the switching of the power transistors M1 and M2.
The output voltage VOUT is coupled to a voltage divider comprised with resistors R1 and R2 through a terminal end FB. The voltage divider generates a feedback voltage VFB to an input end of an error comparator 126 for forming a feedback control loop, and so the buck converting controller 100 switches the power transistors M1 and M2 in response to the feedback voltage VFB. A voltage reference circuit 136 is coupled to the input voltage and provides a reference signal VREF to the other input end of the error comparator 126. The error comparator 126 compares the reference signal VREF and the feedback voltage VFB and accordingly generates an error voltage signal VERR. The error voltage signal VERR is coupled to a starting end Start of an On timer 128 for starting the On process of the On timer 128. At this time, the On timer 128 provides a control signal 129 to a logic circuit 132, and so the logic circuit 132 turns on the power transistor M1 for a constant on time period through the driver 134 for raising the current of the inductance L1. After the power transistor M1 is turned on for the constant on time, the On timer 128 controls the logic circuit 132 through the driver 134 to cutoff the power transistor M1 and turn on the power transistor M2.
For executing the minimum off time control, the On timer 128 provides an end signal at an ending output end End to a starting end Start of an Off timer 130. The Off timer 130 starts the Off time process when the On-time duration expires, and provides an ending signal to the logic circuit 132 to indicate the end of the off-time duration. If the feedback voltage VFB is lower than the reference signal VREF at this time, the logic circuit 132 immediately turns on the power transistor M1 again.
The buck converting controller 100 comprising a ripple injection circuit 120, which is coupled between the switching output voltage VSW (terminal end 122) and the feedback voltage VFB (terminal end FB). A feed-forward capacitance CFF is connected to the output voltage VOUT (the terminal end 114) and the ripple injection circuit 120 (terminal end FFWD). By the above-mentioned circuit structure, a given amount of ripple is injected into the feedback control loop and so the resistance value of the equivalent series resistance of the output capacitance is unlimited.
Although the DC to DC converting circuit with the constant on time shown in FIG. 2 injects ripple into the feedback control loop for ripple compensation, and so the operation frequency can be set high and the MLCC having a smaller equivalent series resistance can be used in the converting circuit. However, the direct current components in the output voltage VOUT have a certain offset voltage due to injecting ripple into the terminal end FFWD. When the output voltage Vout is lower, an influence of the DC offset voltage is especially serious.